[arch-commits] Commit in nouveau-drm/trunk (3 files)
andyrtr at archlinux.org
andyrtr at archlinux.org
Thu Nov 12 17:08:14 UTC 2009
Date: Thursday, November 12, 2009 @ 12:08:14
Author: andyrtr
Revision: 58711
new snapshot 20091111 + much better fix for nv4* tv detection/screen resolution
Added:
nouveau-drm/trunk/tvdac_load_detection.patch
Modified:
nouveau-drm/trunk/PKGBUILD
nouveau-drm/trunk/fix_resolution_detection.patch
--------------------------------+
PKGBUILD | 16 ++---
fix_resolution_detection.patch | 77 +++++++++++++++---------
tvdac_load_detection.patch | 121 +++++++++++++++++++++++++++++++++++++++
3 files changed, 177 insertions(+), 37 deletions(-)
Modified: PKGBUILD
===================================================================
--- PKGBUILD 2009-11-12 13:42:39 UTC (rev 58710)
+++ PKGBUILD 2009-11-12 17:08:14 UTC (rev 58711)
@@ -3,7 +3,7 @@
# Contributor: buddabrod <buddabrod at gmail.com>
pkgname=nouveau-drm
-_snapdate=20091101
+_snapdate=20091111
pkgver=0.0.15_${_snapdate} # see master/drivers/gpu/drm/nouveau/nouveau_drv.h for version
_kernver='2.6.31-ARCH'
pkgrel=1
@@ -19,18 +19,16 @@
#http://people.freedesktop.org/~pq/nouveau-drm/master.tar.gz
# get the Makefile from http://cgit.freedesktop.org/nouveau/linux-2.6/plain/nouveau/Makefile?h=master-compat
Makefile
- fix_resolution_detection.patch)
-md5sums=('bff3fb394cedbf54564cdc242ca49f37'
+ tvdac_load_detection.patch)
+md5sums=('bbd406c6b8d93defbe17d4f4b477b500'
'b619729a9374b7172fc1a7ce59f7f3ad'
- '47382868360f998213fb0e62fed00716')
+ 'bf0f9dcbcecd42f8e8f10b6ee786fb99')
- # http://nouveau.freedesktop.org/wiki/InstallDRM
-
build() {
cd ${srcdir}/master
- # try to fix http://bbs.archlinux.org/viewtopic.php?id=82363 -solved for my nv44 card
- patch -Np0 -i ${srcdir}/fix_resolution_detection.patch || return 1
-
+ # try to fix http://bbs.archlinux.org/viewtopic.php?id=82363
+ patch -Np1 -i ${srcdir}/tvdac_load_detection.patch || return 1
+
mkdir nouveau
cp $srcdir/Makefile ${srcdir}/master/nouveau/
cd nouveau
Modified: fix_resolution_detection.patch
===================================================================
--- fix_resolution_detection.patch 2009-11-12 13:42:39 UTC (rev 58710)
+++ fix_resolution_detection.patch 2009-11-12 17:08:14 UTC (rev 58711)
@@ -1,36 +1,34 @@
---- drivers/gpu/drm/nouveau/nv04_dac.c 2009-10-20 17:54:19.454045092 +0200
-+++ drivers/gpu/drm/nouveau/nv04_dac.c.block3 2009-10-20 18:01:44.891084375 +0200
-@@ -223,6 +223,20 @@
- saved_rtest_ctrl, temp, saved_gpio_ext = 0, routput;
- int head, present = 0;
-
-+nv_wr32(dev, 0x68252c, 0x100); /*363389.094484 write32 #1 NV11_PRAMDAC.OUTPUT_OR_2_3 <- {00000000000000000000000}, OUTPUT_SELECT_CRTC1 = 0x1, {0000000}, OUTPUT_DAC_ENABLE = 0x0*/
-+nv_wr32(dev, 0x68252c, 0x100); /*363391.094548 write32 #1 NV11_PRAMDAC.OUTPUT_OR_2_3 <- {00000000000000000000000}, OUTPUT_SELECT_CRTC1 = 0x1, {0000000}, OUTPUT_DAC_ENABLE = 0x0*/
-+nv_wr32(dev, 0x68252c, 0x101); /*363392.095582 write32 #1 NV11_PRAMDAC.OUTPUT_OR_2_3 <- {00000000000000000000000}, OUTPUT_SELECT_CRTC1 = 0x1, {0000000}, OUTPUT_DAC_ENABLE = 0x1*/
-+nv_wr32(dev, 0x68252c, 0x101); /*363394.095650 write32 #1 NV11_PRAMDAC.OUTPUT_OR_2_3 <- {00000000000000000000000}, OUTPUT_SELECT_CRTC1 = 0x1, {0000000}, OUTPUT_DAC_ENABLE = 0x1*/
-+nv_wr32(dev, 0x68252c, 0x100); /*363396.095714 write32 #1 NV11_PRAMDAC.OUTPUT_OR_2_3 <- {00000000000000000000000}, OUTPUT_SELECT_CRTC1 = 0x1, {0000000}, OUTPUT_DAC_ENABLE = 0x0*/
-+nv_wr32(dev, 0x68252c, 0x101); /*363397.161792 write32 #1 NV11_PRAMDAC.OUTPUT_OR_2_3 <- {00000000000000000000000}, OUTPUT_SELECT_CRTC1 = 0x1, {0000000}, OUTPUT_DAC_ENABLE = 0x1*/
-+nv_wr32(dev, 0x682610, 0x94050140); /*363399.161860 write32 #1 NV11_PRAMDAC[1].TEST_DATA <- 0x94050140*/
-+nv_wr32(dev, 0x682610, 0x94050140); /*363400.161892 write32 #1 NV11_PRAMDAC[1].TEST_DATA <- 0x94050140*/
-+nv_wr32(dev, 0x682608, 0xf0101000); /*363402.161956 write32 #1 NV11_PRAMDAC.TEST_CONTROL_OR_2_3 <- 0xf0101000*/
-+nv_wr32(dev, 0x682608, 0x100000); /*363405.163058 write32 #1 NV11_PRAMDAC.TEST_CONTROL_OR_2_3 <- 0x00100000*/
-+nv_wr32(dev, 0x68252c, 0x100); /*363406.163090 write32 #1 NV11_PRAMDAC.OUTPUT_OR_2_3 <- {00000000000000000000000}, OUTPUT_SELECT_CRTC1 = 0x1, {0000000}, OUTPUT_DAC_ENABLE = 0x0*/
-+
-+msleep(30);
-+
- #define RGB_TEST_DATA(r, g, b) (r << 0 | g << 10 | b << 20)
- if (dcb->type == OUTPUT_TV) {
- testval = RGB_TEST_DATA(0xa0, 0xa0, 0xa0);
-@@ -236,6 +250,8 @@
+diff --git a/drivers/gpu/drm/nouveau/nv04_dac.c b/drivers/gpu/drm/nouveau/nv04_dac.c
+index 587b6f5..3aedd20 100644
+--- a/drivers/gpu/drm/nouveau/nv04_dac.c
++++ b/drivers/gpu/drm/nouveau/nv04_dac.c
+@@ -236,29 +236,42 @@ enum drm_connector_status nv17_dac_detect(struct drm_encoder *encoder,
testval = dev_priv->vbios->dactestval;
}
-+ testval = 0x94050140;
++ nv_wr32(dev, 0x60081c, 0x22255256); /*216780.520000 write32 #1 NV_PCRTC[0].CRTC_081C <- 0x22255256*/
++ nv_wr32(dev, 0x60281c, 0x22255256); /*216781.520033 write32 #1 NV_PCRTC[1].CRTC_081C <- 0x22255256*/
++ nv_wr32(dev, 0x1084, 0x205749); /*216786.521228 write32 #1 NV_PBUS+0x84 <- 0x00205749*/
++ nv_wr32(dev, 0x1588, 0x88802015); /*216796.521681 write32 #1 NV_PBUS+0x588 <- 0x88802015*/
++ nv_wr32(dev, 0x682608, 0x20100000); /*216798.521747 write32 #1 NV11_PRAMDAC.TEST_CONTROL_OR_2_3 <- 0x20100000*/
++ nv_wr32(dev, 0x68252c, 0x111);
++ msleep(10);
+
saved_rtest_ctrl = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset);
NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset,
saved_rtest_ctrl & ~NV_PRAMDAC_TEST_CONTROL_PWRDWN_DAC_OFF);
-@@ -251,8 +267,10 @@
+
+ saved_powerctrl_2 = nvReadMC(dev, NV_PBUS_POWERCTRL_2);
+
+- nvWriteMC(dev, NV_PBUS_POWERCTRL_2, saved_powerctrl_2 & 0xd7ffffff);
++ nvWriteMC(dev, NV_PBUS_POWERCTRL_2, saved_powerctrl_2 /*& 0xd7ffffff */);
+ if (regoffset == 0x68) {
+ saved_powerctrl_4 = nvReadMC(dev, NV_PBUS_POWERCTRL_4);
++#if 0
+ nvWriteMC(dev, NV_PBUS_POWERCTRL_4, saved_powerctrl_4 & 0xffffffcf);
++#endif
+ }
+
if (dev_priv->chipset >= 0x34) {
saved_gpio_ext = NVReadCRTC(dev, 0, NV_PCRTC_GPIO_EXT);
@@ -40,8 +38,17 @@
+#endif
}
- msleep(4);
-@@ -267,13 +285,14 @@
+- msleep(4);
++ msleep(10);
+
+ saved_routput = NVReadRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset);
+- head = (saved_routput & 0x100) >> 8;
++ /* head = (saved_routput & 0x100) >> 8; */
++ head = 1;
+ #if 0
+ /* if there's a spare crtc, using it will minimise flicker for the case
+ * where the in-use crtc is in use by an off-chip tmds encoder */
+@@ -267,13 +280,14 @@ enum drm_connector_status nv17_dac_detect(struct drm_encoder *encoder,
#endif
/* nv driver and nv31 use 0xfffffeee, nv34 and 6600 use 0xfffffece */
routput = (saved_routput & 0xfffffece) | head << 8;
@@ -57,3 +64,17 @@
NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, routput);
msleep(1);
+@@ -286,10 +300,12 @@ enum drm_connector_status nv17_dac_detect(struct drm_encoder *encoder,
+ temp = NVReadRAMDAC(dev, head, NV_PRAMDAC_TEST_CONTROL);
+ NVWriteRAMDAC(dev, head, NV_PRAMDAC_TEST_CONTROL,
+ temp | NV_PRAMDAC_TEST_CONTROL_TP_INS_EN_ASSERTED);
+- msleep(5);
++ msleep(10);
+
+ temp = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset);
+
++ printk("NV_PRAMDAC_TEST_CONTROL + %x: %x\n", regoffset, temp);
++
+ if (dcb->type == OUTPUT_TV)
+ present = (nv17_tv_detect(encoder, connector, (temp >> 28) & 0xe)
+ == connector_status_connected);
Added: tvdac_load_detection.patch
===================================================================
--- tvdac_load_detection.patch (rev 0)
+++ tvdac_load_detection.patch 2009-11-12 17:08:14 UTC (rev 58711)
@@ -0,0 +1,121 @@
+diff --git a/drivers/gpu/drm/nouveau/nv04_dac.c b/drivers/gpu/drm/nouveau/nv04_dac.c
+index 587b6f5..80a1636 100644
+--- a/drivers/gpu/drm/nouveau/nv04_dac.c
++++ b/drivers/gpu/drm/nouveau/nv04_dac.c
+@@ -220,7 +220,8 @@ enum drm_connector_status nv17_dac_detect(struct drm_encoder *encoder,
+ struct dcb_entry *dcb = nouveau_encoder(encoder)->dcb;
+ uint32_t testval, regoffset = nv04_dac_output_offset(encoder);
+ uint32_t saved_powerctrl_2 = 0, saved_powerctrl_4 = 0, saved_routput,
+- saved_rtest_ctrl, temp, saved_gpio_ext = 0, routput;
++ saved_rtest_ctrl, temp, saved_gpio_ext = 0, saved_pcrtc_850 = 0,
++ routput;
+ int head, present = 0;
+
+ #define RGB_TEST_DATA(r, g, b) (r << 0 | g << 10 | b << 20)
+@@ -248,11 +249,31 @@ enum drm_connector_status nv17_dac_detect(struct drm_encoder *encoder,
+ nvWriteMC(dev, NV_PBUS_POWERCTRL_4, saved_powerctrl_4 & 0xffffffcf);
+ }
+
+- if (dev_priv->chipset >= 0x34) {
++ if (nv_arch(dev) >= NV_30) {
+ saved_gpio_ext = NVReadCRTC(dev, 0, NV_PCRTC_GPIO_EXT);
++ printk("PCRTC[0]+GPIO_EXT: %x\n", saved_gpio_ext);
++ }
++
++ if (nv_arch(dev) >= NV_40) {
++ saved_pcrtc_850 = NVReadCRTC(dev, 0, NV_PCRTC_850);
++ printk("PCRTC[0]+850: %x\n", saved_pcrtc_850);
++
++ }
+
+- NVWriteCRTC(dev, 0, NV_PCRTC_GPIO_EXT, (saved_gpio_ext & ~(3 << 20)) |
++ if ((dev_priv->chipset >= 0x34 && dev_priv->chipset < 0x44) ||
++ (nv_arch(dev) == NV_30 && !dev_priv->VBIOS.is_mobile)) {
++ NVWriteCRTC(dev, 0, NV_PCRTC_GPIO_EXT,
++ (saved_gpio_ext & ~(3 << 20)) |
+ (dcb->type == OUTPUT_TV ? (1 << 20) : 0));
++
++ } else if (dev_priv->chipset >= 0x44) {
++ NVWriteCRTC(dev, 0, NV_PCRTC_850,
++ (saved_pcrtc_850 & ~0xf0) |
++ (dcb->type == OUTPUT_TV ? 0x50 : 0x00));
++
++ NVWriteCRTC(dev, 0, NV_PCRTC_GPIO_EXT,
++ (saved_gpio_ext & ~0xf0) |
++ (dcb->type == OUTPUT_TV ? 0x50 : 0x00));
+ }
+
+ msleep(4);
+@@ -268,7 +289,7 @@ enum drm_connector_status nv17_dac_detect(struct drm_encoder *encoder,
+ /* nv driver and nv31 use 0xfffffeee, nv34 and 6600 use 0xfffffece */
+ routput = (saved_routput & 0xfffffece) | head << 8;
+
+- if (nv_arch(dev) >= NV_40) {
++ if (dev_priv->chipset >= 0x4b) {
+ if (dcb->type == OUTPUT_TV)
+ routput |= 1 << 20;
+ else
+@@ -289,6 +310,7 @@ enum drm_connector_status nv17_dac_detect(struct drm_encoder *encoder,
+ msleep(5);
+
+ temp = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset);
++ printk("NV_PRAMDAC_TEST_CONTROL + %x: %x\n", regoffset, temp);
+
+ if (dcb->type == OUTPUT_TV)
+ present = (nv17_tv_detect(encoder, connector, (temp >> 28) & 0xe)
+@@ -308,8 +330,11 @@ enum drm_connector_status nv17_dac_detect(struct drm_encoder *encoder,
+ nvWriteMC(dev, NV_PBUS_POWERCTRL_4, saved_powerctrl_4);
+ nvWriteMC(dev, NV_PBUS_POWERCTRL_2, saved_powerctrl_2);
+
+- if (dev_priv->chipset >= 0x34)
+- NVWriteRAMDAC(dev, 0, NV_PCRTC_GPIO_EXT, saved_gpio_ext);
++ if (nv_arch(dev) >= NV_30)
++ NVWriteCRTC(dev, 0, NV_PCRTC_GPIO_EXT, saved_gpio_ext);
++
++ if (nv_arch(dev) >= NV_40)
++ NVWriteCRTC(dev, 0, NV_PCRTC_850, saved_pcrtc_850);
+
+ if (present) {
+ NV_INFO(dev, "Load detected on output %c\n", '@' + ffs(dcb->or));
+diff --git a/drivers/gpu/drm/nouveau/nv17_tv.c b/drivers/gpu/drm/nouveau/nv17_tv.c
+index 34f95c7..0c125e1 100644
+--- a/drivers/gpu/drm/nouveau/nv17_tv.c
++++ b/drivers/gpu/drm/nouveau/nv17_tv.c
+@@ -237,14 +237,20 @@ static void nv17_tv_dpms(struct drm_encoder *encoder, int mode)
+
+ nv_load_ptv(dev, regs, 200);
+
+- if (dev_priv->chipset >= 0x34) {
+- uint32_t *gpio_ext = &dev_priv->mode_reg.crtc_reg[0].gpio_ext;
+-
+- *gpio_ext &= ~(3 << 20);
+- if (mode == DRM_MODE_DPMS_ON)
+- *gpio_ext |= 1 << 20;
+-
+- NVWriteCRTC(dev, 0, NV_PCRTC_GPIO_EXT, *gpio_ext);
++ if ((dev_priv->chipset >= 0x34 && dev_priv->chipset < 0x44) ||
++ (nv_arch(dev) == NV_30 && !dev_priv->VBIOS.is_mobile)) {
++ NVWriteCRTC(dev, 0, NV_PCRTC_GPIO_EXT,
++ (dev_priv->mode_reg.crtc_reg[0].gpio_ext & ~(3 << 20)) |
++ (mode == DRM_MODE_DPMS_ON ? (1 << 20) : 0));
++
++ } else if (dev_priv->chipset >= 0x44) {
++ NVWriteCRTC(dev, 0, NV_PCRTC_850,
++ (NVReadCRTC(dev, 0, NV_PCRTC_850) & ~0xf0) |
++ (mode == DRM_MODE_DPMS_ON ? 0x50 : 0x00));
++
++ NVWriteCRTC(dev, 0, NV_PCRTC_GPIO_EXT,
++ (dev_priv->mode_reg.crtc_reg[0].gpio_ext & ~0xf0) |
++ (mode == DRM_MODE_DPMS_ON ? 0x50 : 0x00));
+ }
+
+ nv04_dac_update_dacclk(encoder, mode == DRM_MODE_DPMS_ON);
+@@ -299,7 +305,7 @@ static void nv17_tv_prepare(struct drm_encoder *encoder)
+ /* Set the DACCLK register */
+ dacclk = (NVReadRAMDAC(dev, 0, dacclk_off) & ~0x30) | 0x1;
+
+- if (nv_arch(dev) == NV_40)
++ if (dev_priv->chipset >= 0x4b)
+ dacclk |= 1 << 20;
+
+ if (tv_norm->kind == CTV_ENC_MODE) {
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