[arch-commits] Commit in llvm/trunk (PKGBUILD disable-bswap-for-spir.patch)

[Evangelos Foutras]

    Date: Wednesday, October 27, 2021 @ 06:13:53
  Author: foutrelis
Revision: 426677

upgpkg: llvm 13.0.0-2: fix an ISPC build failure

https://github.com/ispc/ispc/issues/2189

Added:
  llvm/trunk/disable-bswap-for-spir.patch
Modified:
  llvm/trunk/PKGBUILD

------------------------------+
 PKGBUILD                     |    7 ++++-
 disable-bswap-for-spir.patch |   50 +++++++++++++++++++++++++++++++++++++++++
 2 files changed, 56 insertions(+), 1 deletion(-)

Modified: PKGBUILD
===================================================================
--- PKGBUILD	2021-10-27 01:22:28 UTC (rev 426676)
+++ PKGBUILD	2021-10-27 06:13:53 UTC (rev 426677)
@@ -3,7 +3,7 @@
 
 pkgname=('llvm' 'llvm-libs' 'llvm-ocaml')
 pkgver=13.0.0
-pkgrel=1
+pkgrel=2
 _ocaml_ver=4.12.0
 arch=('x86_64')
 url="https://llvm.org/"
@@ -16,10 +16,12 @@
 _source_base=https://github.com/llvm/llvm-project/releases/download/llvmorg-$pkgver
 source=($_source_base/$pkgname-$pkgver.src.tar.xz{,.sig}
         no-strict-aliasing-DwarfCompileUnit.patch
+        disable-bswap-for-spir.patch
         llvm-config.h)
 sha256sums=('408d11708643ea826f519ff79761fcdfc12d641a2510229eec459e72f8163020'
             'SKIP'
             'd1eff24508e35aae6c26a943dbaa3ef5acb60a145b008fd1ef9ac6f6c4faa662'
+            'af163392fbc19d65d11ab4b1510a2eae39b417d6228023b3ba5395b138bb41f5'
             '597dc5968c695bbdbb0eac9e8eb5117fcd2773bc91edf5ec103ecffffab8bc48')
 validpgpkeys+=('B6C8F98282B944E3B0D5C2530FC3042E345AD05D') # Hans Wennborg <hans at chromium.org>
 validpgpkeys+=('474E22316ABF4785A88C6E8EA2C794A986419D8A') # Tom Stellard <tstellar at redhat.com>
@@ -31,6 +33,9 @@
   # Work around intermittent 'clang -O -g' crashes
   # https://bugs.llvm.org/show_bug.cgi?id=50611#c3
   patch -Np2 -i ../no-strict-aliasing-DwarfCompileUnit.patch
+
+  # Fix an ISPC build failure (https://github.com/ispc/ispc/issues/2189)
+  patch -Np2 -i ../disable-bswap-for-spir.patch
 }
 
 build() {

Added: disable-bswap-for-spir.patch
===================================================================
--- disable-bswap-for-spir.patch	                        (rev 0)
+++ disable-bswap-for-spir.patch	2021-10-27 06:13:53 UTC (rev 426677)
@@ -0,0 +1,50 @@
+# Based on https://github.com/ispc/ispc/blob/main/llvm_patches/12_0_disable-A-B-A-B-and-BSWAP-in-InstCombine.patch
+
+diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
+index d01a021bf3f4..bccce825a03d 100644
+--- a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
++++ b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
+@@ -15,6 +15,7 @@
+ #include "llvm/ADT/APInt.h"
+ #include "llvm/ADT/STLExtras.h"
+ #include "llvm/ADT/SmallVector.h"
++#include "llvm/ADT/Triple.h"
+ #include "llvm/Analysis/InstructionSimplify.h"
+ #include "llvm/Analysis/ValueTracking.h"
+ #include "llvm/IR/Constant.h"
+@@ -1369,9 +1370,12 @@ Instruction *InstCombinerImpl::visitAdd(BinaryOperator &I) {
+     }
+   }
+ 
+-  // A+B --> A|B iff A and B have no bits set in common.
+-  if (haveNoCommonBitsSet(LHS, RHS, DL, &AC, &I, &DT))
+-    return BinaryOperator::CreateOr(LHS, RHS);
++  // Disable this transformation for ISPC SPIR-V
++  if (!Triple(I.getModule()->getTargetTriple()).isSPIR()) {
++    // A+B --> A|B iff A and B have no bits set in common.
++    if (haveNoCommonBitsSet(LHS, RHS, DL, &AC, &I, &DT))
++      return BinaryOperator::CreateOr(LHS, RHS);
++  }
+ 
+   // add (select X 0 (sub n A)) A  -->  select X A n
+   {
+diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
+index 120852c44474..8de55311ce3e 100644
+--- a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
++++ b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
+@@ -2671,9 +2671,12 @@ Instruction *InstCombinerImpl::visitOr(BinaryOperator &I) {
+   if (Instruction *FoldedLogic = foldBinOpIntoSelectOrPhi(I))
+     return FoldedLogic;
+ 
+-  if (Instruction *BitOp = matchBSwapOrBitReverse(I, /*MatchBSwaps*/ true,
+-                                                  /*MatchBitReversals*/ true))
+-    return BitOp;
++  // Disable this transformation for ISPC SPIR-V
++  if (!Triple(I.getModule()->getTargetTriple()).isSPIR()) {
++    if (Instruction *BitOp = matchBSwapOrBitReverse(I, /*MatchBSwaps*/ true,
++                                                    /*MatchBitReversals*/ true))
++      return BitOp;
++  }
+ 
+   if (Instruction *Funnel = matchFunnelShift(I, *this))
+     return Funnel;