[arch-commits] Commit in llvm/trunk (4 files)
Evangelos Foutras
foutrelis at gemini.archlinux.org
Sun May 15 20:17:46 UTC 2022
Date: Sunday, May 15, 2022 @ 20:17:45
Author: foutrelis
Revision: 445846
upgpkg: llvm 13.0.1-3: add another patch for ISPC
Added:
llvm/trunk/disable-A-B-A-B-and-BSWAP-in-InstCombine.patch
llvm/trunk/disable-DIArgList-in-SPIR-V.patch
Modified:
llvm/trunk/PKGBUILD
Deleted:
llvm/trunk/disable-bswap-for-spir.patch
------------------------------------------------+
PKGBUILD | 13 +++--
disable-A-B-A-B-and-BSWAP-in-InstCombine.patch | 52 +++++++++++++++++++++++
disable-DIArgList-in-SPIR-V.patch | 23 ++++++++++
disable-bswap-for-spir.patch | 50 ----------------------
4 files changed, 83 insertions(+), 55 deletions(-)
Modified: PKGBUILD
===================================================================
--- PKGBUILD 2022-05-15 19:53:26 UTC (rev 445845)
+++ PKGBUILD 2022-05-15 20:17:45 UTC (rev 445846)
@@ -3,7 +3,7 @@
pkgname=('llvm' 'llvm-libs' 'llvm-ocaml')
pkgver=13.0.1
-pkgrel=2
+pkgrel=3
_ocaml_ver=4.13.1
arch=('x86_64')
url="https://llvm.org/"
@@ -18,7 +18,8 @@
don-t-accept-nullptr-as-GEP-element-type.patch
don-t-move-DBG_VALUE-instructions.patch
no-strict-aliasing-DwarfCompileUnit.patch
- disable-bswap-for-spir.patch
+ disable-A-B-A-B-and-BSWAP-in-InstCombine.patch
+ disable-DIArgList-in-SPIR-V.patch
llvm-config.h)
sha256sums=('ec6b80d82c384acad2dc192903a6cf2cdbaffb889b84bfb98da9d71e630fc834'
'SKIP'
@@ -25,7 +26,8 @@
'a7e902a7612d0fdabe436a917468b043cc296bc89d8954bfc3126f737beb9ac4'
'f7d69f84241416398fdb3df8bb44f9fae3c49d89889c7ffa3b37aa2e9d78f708'
'd1eff24508e35aae6c26a943dbaa3ef5acb60a145b008fd1ef9ac6f6c4faa662'
- 'af163392fbc19d65d11ab4b1510a2eae39b417d6228023b3ba5395b138bb41f5'
+ '34cc0d79a30599cb2287b47b4e9a1a5bf03d57a1f8bb35be3fe976ffc4a604f6'
+ '8642da2d556092e4284873ba6ddc6c9a67841f42cc16f923bcd523e4b304a3ff'
'597dc5968c695bbdbb0eac9e8eb5117fcd2773bc91edf5ec103ecffffab8bc48')
validpgpkeys+=('B6C8F98282B944E3B0D5C2530FC3042E345AD05D') # Hans Wennborg <hans at chromium.org>
validpgpkeys+=('474E22316ABF4785A88C6E8EA2C794A986419D8A') # Tom Stellard <tstellar at redhat.com>
@@ -45,8 +47,9 @@
# https://bugs.llvm.org/show_bug.cgi?id=50611#c3
patch -Np2 -i ../no-strict-aliasing-DwarfCompileUnit.patch
- # Fix an ISPC build failure (https://github.com/ispc/ispc/issues/2189)
- patch -Np2 -i ../disable-bswap-for-spir.patch
+ # Patches needed for ISPC for Xe only
+ patch -Np2 -i ../disable-A-B-A-B-and-BSWAP-in-InstCombine.patch
+ patch -Np2 -i ../disable-DIArgList-in-SPIR-V.patch
}
build() {
Added: disable-A-B-A-B-and-BSWAP-in-InstCombine.patch
===================================================================
--- disable-A-B-A-B-and-BSWAP-in-InstCombine.patch (rev 0)
+++ disable-A-B-A-B-and-BSWAP-in-InstCombine.patch 2022-05-15 20:17:45 UTC (rev 445846)
@@ -0,0 +1,52 @@
+# This patch is needed for ISPC for Xe only
+
+# 1. Transformation of add to or is not safe for VC backend.
+# 2. bswap intrinsics is not supported in VC backend yet.
+diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
+index d01a021bf3f4..bccce825a03d 100644
+--- a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
++++ b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
+@@ -15,6 +15,7 @@
+ #include "llvm/ADT/APInt.h"
+ #include "llvm/ADT/STLExtras.h"
+ #include "llvm/ADT/SmallVector.h"
++#include "llvm/ADT/Triple.h"
+ #include "llvm/Analysis/InstructionSimplify.h"
+ #include "llvm/Analysis/ValueTracking.h"
+ #include "llvm/IR/Constant.h"
+@@ -1369,9 +1370,12 @@ Instruction *InstCombinerImpl::visitAdd(BinaryOperator &I) {
+ }
+ }
+
+- // A+B --> A|B iff A and B have no bits set in common.
+- if (haveNoCommonBitsSet(LHS, RHS, DL, &AC, &I, &DT))
+- return BinaryOperator::CreateOr(LHS, RHS);
++ // Disable this transformation for ISPC SPIR-V
++ if (!Triple(I.getModule()->getTargetTriple()).isSPIR()) {
++ // A+B --> A|B iff A and B have no bits set in common.
++ if (haveNoCommonBitsSet(LHS, RHS, DL, &AC, &I, &DT))
++ return BinaryOperator::CreateOr(LHS, RHS);
++ }
+
+ // add (select X 0 (sub n A)) A --> select X A n
+ {
+diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
+index 120852c44474..8de55311ce3e 100644
+--- a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
++++ b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
+@@ -2671,9 +2671,12 @@ Instruction *InstCombinerImpl::visitOr(BinaryOperator &I) {
+ if (Instruction *FoldedLogic = foldBinOpIntoSelectOrPhi(I))
+ return FoldedLogic;
+
+- if (Instruction *BitOp = matchBSwapOrBitReverse(I, /*MatchBSwaps*/ true,
+- /*MatchBitReversals*/ true))
+- return BitOp;
++ // Disable this transformation for ISPC SPIR-V
++ if (!Triple(I.getModule()->getTargetTriple()).isSPIR()) {
++ if (Instruction *BitOp = matchBSwapOrBitReverse(I, /*MatchBSwaps*/ true,
++ /*MatchBitReversals*/ true))
++ return BitOp;
++ }
+
+ if (Instruction *Funnel = matchFunnelShift(I, *this))
+ return Funnel;
Added: disable-DIArgList-in-SPIR-V.patch
===================================================================
--- disable-DIArgList-in-SPIR-V.patch (rev 0)
+++ disable-DIArgList-in-SPIR-V.patch 2022-05-15 20:17:45 UTC (rev 445846)
@@ -0,0 +1,23 @@
+# This patch is needed for ISPC for Xe only
+# It disables using of DIArgList for dbg.val if SPIR-V target is used.
+# It is needed till DIArgList is supported in SPIR-V Translator.
+diff --git a/llvm/lib/Transforms/Utils/Local.cpp b/llvm/lib/Transforms/Utils/Local.cpp
+index d03d76f57ca1..0b86e454df57 100644
+--- a/llvm/lib/Transforms/Utils/Local.cpp
++++ b/llvm/lib/Transforms/Utils/Local.cpp
+@@ -1771,7 +1771,14 @@ void llvm::salvageDebugInfoForDbgValues(
+ } else if (isa<DbgValueInst>(DII) &&
+ DII->getNumVariableLocationOps() + AdditionalValues.size() <=
+ MaxDebugArgs) {
+- DII->addVariableLocationOps(AdditionalValues, SalvagedExpr);
++ if (!Triple(I.getModule()->getTargetTriple()).isSPIR()) {
++ DII->addVariableLocationOps(AdditionalValues, SalvagedExpr);
++ } else {
++ // Do not salvage using DIArgList for dbg.val fpr SPIR-V target, as it is
++ // not currently supported by SPIR-V Translator.
++ Value *Undef = UndefValue::get(I.getOperand(0)->getType());
++ DII->replaceVariableLocationOp(I.getOperand(0), Undef);
++ }
+ } else {
+ // Do not salvage using DIArgList for dbg.addr/dbg.declare, as it is
+ // currently only valid for stack value expressions.
Deleted: disable-bswap-for-spir.patch
===================================================================
--- disable-bswap-for-spir.patch 2022-05-15 19:53:26 UTC (rev 445845)
+++ disable-bswap-for-spir.patch 2022-05-15 20:17:45 UTC (rev 445846)
@@ -1,50 +0,0 @@
-# Based on https://github.com/ispc/ispc/blob/main/llvm_patches/12_0_disable-A-B-A-B-and-BSWAP-in-InstCombine.patch
-
-diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
-index d01a021bf3f4..bccce825a03d 100644
---- a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
-+++ b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
-@@ -15,6 +15,7 @@
- #include "llvm/ADT/APInt.h"
- #include "llvm/ADT/STLExtras.h"
- #include "llvm/ADT/SmallVector.h"
-+#include "llvm/ADT/Triple.h"
- #include "llvm/Analysis/InstructionSimplify.h"
- #include "llvm/Analysis/ValueTracking.h"
- #include "llvm/IR/Constant.h"
-@@ -1369,9 +1370,12 @@ Instruction *InstCombinerImpl::visitAdd(BinaryOperator &I) {
- }
- }
-
-- // A+B --> A|B iff A and B have no bits set in common.
-- if (haveNoCommonBitsSet(LHS, RHS, DL, &AC, &I, &DT))
-- return BinaryOperator::CreateOr(LHS, RHS);
-+ // Disable this transformation for ISPC SPIR-V
-+ if (!Triple(I.getModule()->getTargetTriple()).isSPIR()) {
-+ // A+B --> A|B iff A and B have no bits set in common.
-+ if (haveNoCommonBitsSet(LHS, RHS, DL, &AC, &I, &DT))
-+ return BinaryOperator::CreateOr(LHS, RHS);
-+ }
-
- // add (select X 0 (sub n A)) A --> select X A n
- {
-diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
-index 120852c44474..8de55311ce3e 100644
---- a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
-+++ b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
-@@ -2671,9 +2671,12 @@ Instruction *InstCombinerImpl::visitOr(BinaryOperator &I) {
- if (Instruction *FoldedLogic = foldBinOpIntoSelectOrPhi(I))
- return FoldedLogic;
-
-- if (Instruction *BitOp = matchBSwapOrBitReverse(I, /*MatchBSwaps*/ true,
-- /*MatchBitReversals*/ true))
-- return BitOp;
-+ // Disable this transformation for ISPC SPIR-V
-+ if (!Triple(I.getModule()->getTargetTriple()).isSPIR()) {
-+ if (Instruction *BitOp = matchBSwapOrBitReverse(I, /*MatchBSwaps*/ true,
-+ /*MatchBitReversals*/ true))
-+ return BitOp;
-+ }
-
- if (Instruction *Funnel = matchFunnelShift(I, *this))
- return Funnel;
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